As the integration density of integrated circuit semiconductor devices continues to increase, it may be increasingly difficult to isolate microelectronic devices such as transistors, from one another, when they are formed in bulk semiconductor substrates such as bulk silicon semiconductor substrates. Semiconductor-on-Insulator (SOI) technology has been proposed as an alternative to bulk semiconductor technology. In SOI technology a thin semiconductor layer is formed on a substrate, which may be a semiconductor substrate, with an intervening insulator layer therebetween. Microelectronic devices such as transistors are formed in the thin semiconductor layer, which may be referred to as an active semiconductor layer or an active layer. Often the active semiconductor layer comprises a thin monocrystalline silicon layer, the insulating layer comprises a silicon oxide layer, and the substrate is a monocrystalline silicon substrate. However, other substrates, insulating layers and active semiconductor layers may be used.
Hereinafter, conventional methods for fabricating an SOI substrate will be described with reference to FIGS. 1A to 1F.
Referring to FIGS. 1A and 1B, a base wafer W1 and a bonding wafer W2 are prepared. The base wafer W1 includes a silicon substrate 10 and an oxidation layer 11 formed on the silicon substrate 10. The bonding wafer W2 includes a silicon substrate 20, and an isolation layer 21 and a silicon layer 22 stacked on the silicon substrate 20 in sequence. The isolation layer 21 may be formed of various materials. For example, the isolation layer 21 may be formed of a porous silicon layer or an ion-implanted silicon layer.
Referring to FIG. 1C, thermal treatment is performed while the oxidation layer 11 of the base wafer W1 and the silicon layer 22 of the bonding wafer W2 are contacted to each other to thereby bond the base wafer W1 and the bonding wafer W2.
Referring to FIG. 1D, the silicon substrate 20 of the bonding wafer W2 is isolated from the base wafer W1 by removing the isolation layer 21, and the surface of the silicon layer 22 is polished.
In accordance with the above-mentioned procedure, an SOI substrate including the silicon substrate 10, the oxidation layer 11, and the silicon layer 22, is prepared. The silicon layer 22 acts as an active semiconductor layer where active elements such as MOS transistors are formed. Thus, the thickness of the silicon layer 22 affects the performance of the MOS transistors. For example, the thickness of the silicon layer 22 may be reduced in order to potentially improve short channel effects of the MOS transistors.
Referring to FIG. 1E, the silicon layer 22 is thermally oxidized to thereby form a thermal oxidation layer 13 on the surface of the silicon layer 22. As a result, the thickness of the silicon layer 22 is reduced so that a silicon layer 22a thinner than the silicon layer 22 can be obtained.
Referring to FIG. 1F, the thermal oxidation layer 13 is removed to expose the silicon layer 22a. The final thickness of the silicon layer 22a may be determined by the thermal oxidation processing time or the number of the repeating thermal oxidation process.
The above-mentioned conventional method for fabricating the SOI substrate adjusts the thickness of the silicon layer 22 by forming and removing the thermal oxidation layer on the surface of the silicon layer 22, so that the thickness may be difficult to control, and in addition, the silicon layer may be largely consumed. Thus, the method may not be desirable for mass production because the manufacturing cost may increase.
Moreover, in the conventional method for fabricating the SOI substrate, in order to perform processes of reducing the isolation layer 21 and polishing the silicon layer 22, the silicon layer 22 should be formed to have at least a minimum thickness. However, a wafer having a large diameter may have a large temperature difference according to the area of its surface, a high degree of bending, and/or a uniformity difference when polishing, oxidation and/or etching processes are performed, compared to a wafer having a small diameter. In particular, the thinner the silicon layer, the greater the uniformity variation may become, so that the thickness difference over the wafer may be excessive. The thickness difference over the area of the wafer may still be present after the polishing and oxidation processes of the silicon layer 22, so that it may become more difficult to obtain the thin and uniform silicon layer 22a. 